1. Field
One or more embodiments of the following description relate to transaction processing on a System-on-Chip (SoC) platform, and more particularly, to a method and apparatus that may improve a memory transmission efficiency on a SoC platform including an Image Signal Processor (ISP).
2. Description of the Related Art
To sequentially apply a precharge command and an active command, when a Synchronous Dynamic Random Access Memory (SDRAM) is accessed, a latency of several clock cycles may occur
The SDRAM has a plurality of banks, namely, independent memory cores. The plurality of banks may share a control signal and a data signal. There is no delay between applying a precharge command to one bank and applying an active command to another bank. In other words, a delay occurring when accessing the SDRAM may be minimized by interleaving the plurality of banks.
However, since a transaction for processing a High Definition (HD) image has a large size, a memory bank interleaving of a transaction unit has limitations in reducing latency.
Additionally, to maximize an effect of bank interleaving, different banks may be targeted by memory accesses that are sequentially adjacent to each other, which may not be possible on a system.